Altera at 40 nm: Jitter, Signal Integrity, Power, and Process Optimized

5. Mixed Signal Clock Recovery 12 5.1 Hybrid (Digitally Assisted) Clock Recovery 12 5.2 Capability Comparisons 12 5.2.1 Jitter Tolerance 12 5.2.2 Flexibility and Versatility 13 5.2.3 Transition Density and Maximum Run Length (MRL) 14 5.2.4 Lock Time 14 6. End-to-End Equalization 15 6.1 Motivation 15 6.2 Equalization in a Nutshell 17 6.3 Types of Signal Conditioning 18 6.3.1 Transmit Pre-Emphasis/De-Emphasis 18 6.3.2 Continuous Time Linear Equalizer 20 6.3.3 Transversal FIR (TFIR) 21 6.3.4 Decision Feedback Equalization 21 6.4 Backplanes and Their Impact on Equalization Selection 22 6.4.1 Backplanes and Equalization Selection 23 6.4.2 The Need for Adaptive Equalization 26 6.4.3 System Development Stages 27 6.5 A Historical Overview of Altera’s Equalization Solutions 28 6.6 Built-In Oscilloscope 28